1. Technical Field
The present invention relates in general to asynchronous logic circuits, and in particular, to an asynchronous control circuit. More particularly, the present invention relates to a tag logic interface for introducing synchronous control signals within an asynchronous pipeline.
2. Description of the Related Art
Improvements in microprocessor performance are often measured in terms of instructions per cycle divided by cycle time. In such terms, microprocessor performance may be improved by either increasing the amount of useful work per cycle or by reducing cycle time. The total amount of work per cycle can be increased by executing multiple instructions in parallel and by avoiding stall conditions through speculation and out-of-order processing.
Increasing processor frequency is commonly achieved through either improvements in Complementary Metal Oxide Semiconductor (CMOS) devices or by adding processing stages within the processing architecture to reduce the amount of processing work per stage, or equivalently, per cycle. In comparison with most microarchitectural mechanisms that aim to increase the amount of work per cycle, improving system frequency imparts a more predictable benefit to overall system performance and therefore resonates more strongly in the marketplace.
At some point, however, performance benefits derived from both the improvements in micro-device design and reduction in logic levels begin to diminish. Increasing power dissipation requirements and increasing leakage currents provide some indication that CMOS technology is reaching its limits.
Pipelining is a well-known technique for improving processor performance. Pipelining is commonly utilized for decomposing a data processing operation into multiple concurrently operating stages to increase throughput at the cost of a moderate increase in latency and logic overhead. A wide variety of applications, such as digital signal processors, video processors, as well as general purpose processors can take advantage of pipeline architecture. Each of these applications may advantageously utilize pipelining to process data in stages where the processing result of one stage is passed to a subsequent stage for further processing. A pipeline consists of multiple processing stages that are connected together into a series of stages with the stages operating on data as the data passes along from one stage to the next.
There are a variety of distinctions among pipeline processors. One distinction being whether the pipelined stages operate in unison in accordance with an external global clock (a synchronous pipeline), or operate independently based on local events (an asynchronous pipeline).
In synchronous pipelines, synchronization of the different processing stages requires that the frequency of the global control clock accommodate the foreseeable worst-case delay for the slowest processing stage. Thus, in a synchronous pipeline design, some processing stages will complete respective operations earlier than other stages and must then wait for all processing stages to complete their operations. The speed of synchronous processing is directly controlled by the global clock frequency and thus can be increased by increasing the speed of the global clock.
A problem with increasing the synchronous clock frequency is clock skew. A circuit can operate synchronously only if all parts of the circuit receive a clock signal at the same time. However, clock signals are delayed as they propagate through the system and, even on a single chip, clock skew is a problem at higher frequencies. Additionally, as cycle time is reduced, synchronous pipeline efficiency is also reduced due to the constant clocking and latching overhead per cycle.
Asynchronous pipelines avoid worst-case timing and clock skew problems since they include no external clock to govern the timing of state changes among the pipelined stages. Instead, asynchronous stages exchange data at mutually negotiated times with no external timing regulation. More specifically, these mutually negotiated exchanges are locally synchronized using event-driven communication in which logic transitions on control lines act to request the start of a transfer and acknowledge its completion. By removing the global clock, asynchronous pipelines have the advantage of elimination of clock skew problems, freedom from worst-case design restrictions, and automatic power-down of unused circuitry.
A “micropipeline” is a common asynchronous pipeline design invented by Ivan Sutherland as set forth in U.S. Pat. No. 4,837,740 and U.S. Pat. No. 5,187,800, the pertinent portions of which are incorporated herein by reference. The approach in Sutherland's micropipeline utilizes bundled data with a transition-signaled handshake protocol to control data transfers.
An “asynchronous interlocked pipeline” is an alternate design discussed in detail in the ISSCC Conference, paper WA 17.3, titled “Asynchronous Interlocked Pipelined CMOS Circuits,” incorporated herein by reference. This type of pipeline circuitry utilizes latches to divide up the pipeline, wherein as with Sutherland's micropipeline, local handshaking replaces global clocking.
Asynchronous pipelines work well as an island of logic but at some point the asynchronous logic must interact with the overall synchronous design. Such interaction is problematic because the variable delay through asynchronous pipelines results in timing mismatches with synchronous latches.
One known solution to asynchronous/synchronous interfacing employs a synchronous delay chain. A number of synchronously controlled latches are connected in series with the number of latches in the chain being determined in accordance with the worst-case anticipated delay through the asynchronous pipeline. When data is sent through the asynchronous pipeline, a valid bit is simultaneously sent through the delay chain as a point of reference for when the synchronous logic can expect the asynchronous data to arrive. Such an interface technique suffers the obvious disadvantage of using the worst-case asynchronous delay as a timing limitation.
From the foregoing, it can be appreciated that a need exists within an asynchronous pipeline architecture for an improved interface between asynchronous and synchronous logic that would permit external management of asynchronous data as it travels through an asynchronous pipeline.